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SE1000W
LightChargerTM155 Mb/s Transimpedance Amplifier Final
Applications
SONET/SDH-based transmission systems, test equipment and modules OC-3 fibre optic modules and line termination ATM and FDDI optical receivers
Product Description
SiGe Semiconductor offers a portfolio of optical networking ICs for use in high-performance optical transmitter and receiver functions, from 155 Mb/s up to 12.5 Gb/s. SiGe Semiconductor's SE1000W is a fully integrated, silicon bipolar transimpedance amplifier; providing wideband, low noise preamplification of signal current from a photodetector. It features single-ended or differential outputs, selectable by wire bond options, and incorporates an automatic gain control mechanism to increase dynamic range, allowing input signals up to 2.6 mA peak. For differential outputs, a decoupling capacitor on the supply is the only external circuitry required. Noise performance is optimized for 155 Mb/s operation, with a calculated rms noise based -10 sensitivity of -41 dBm for 10 bit error rate, achieved using a detector with 0.5 pF capacitance and a responsivity of 0.95 A/W, with an infinite extinction ratio source.
Features
Single +5 V power supply Input noise current = 12 nA rms when used with a 0.5 pF detector Transimpedance gain = 15 k into a 50 load (single-ended) On-chip automatic gain control gives input current overload of 2.6 mA pk and max output voltage swing of 300 mV pk-pk 50 single-ended or 100 differential wire bond selectable outputs Bandwidth (-3 dB) = 150 MHz (min) Wide data rate range = 10 Mb/s to 155 Mb/s High input bias level = 2 V Minimal external components, supply decoupling only Operating junction temperature range = -40C to +95C Equivalent to Nortel Networks AB52

Ordering Information
Type SE1000W Package Bare Die Remark Shipped in Waffle Pack
Functional Block Diagram
SE1000 TzAmp 155 Mb/s
Automatic Gain Control
Integrator
Rectifier
Rf TZ_IN Input Current Tz Amp Output Driver
50 50 50
OUTP OUTN
Bandgap Reference
Power Supply Rejection
GND or -ve supply
ACGND Wire bond option for single-ended operation
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Bondpad Diagram
VCC2
1
10
VCC1
VCC1
2
Top View
9 TZ_IN 3 8 OUTN OUTP
4 VEE2
5 ACGND
6 VEE1
7 VEE1
Bondpad Description
Pad No. 1 2 3 4 5 6 7 8 9 10 Name VCC2 VCC1 TZ_IN VEE2 ACGND VEE1 VEE1 OUTN OUTP VCC1 Description Positive supply (+5.0 V), front end circuitry only. Positive supply (+5.0 V), pads 2 & 10 are connected on chip. Only one pad needs to be bonded. Input pad (connect to photodetector cathode). Negative supply (0V) - Note this is separate ground for the input stage, which is AC coupled on chip. There is no DC current through this pad. Bond option: Connected to external capacitor to ground for single-ended operation (recommended 1 nF); unconnected for differential operation. Negative supply (0V), pads 6 & 7are connected on chip. Only one pad needs to be bonded. Negative supply (0V), pads 6 & 7 are connected on chip. Only one pad needs to be bonded. Negative differential voltage output; leave unconnected for single-ended operation. Positive differential or single-ended voltage output. Positive supply (+5.0 V), pads 2 & 10 are connected on chip. Only one pad needs to be bonded.
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Functional Description Amplifier Front-End
The transimpedance front-end amplifies an input current from a photodetector, at pin TZ_IN, to produce an output voltage with the feedback resistor Rf determining the level of amplification (see the functional block diagram on page 1). An automatic gain control loop varies this resistor, to ensure that the output from the front-end does not saturate the output driver stage that follows. This gain control allows input signals of up to 2.6 mA peak. The input pin TZ_IN is biased at 3 V below the supply voltage VCC, allowing a photodetector to easily be reverse biased by connecting the anode to ground, and hence enabling s ingle rail operation. The front-end stage has its own supply pins, VCC2 (+5 V) and VEE2 (0 V), to achieve optimum noise performance and maintain integrity of the high-speed signal path. The remainder of the circuitry uses the supply pins VCC1 (+5 V) and VEE1 (0 V).
to ground (recommend 1 nF). Under these circumstances, OUTP operates as a single-ended 50 output. In both cases, increasing optical input level gives a positive-going output signal on the OUTP pin.
Automatic Gain Control (AGC)
The AGC circuit monitors the voltages from the output driver and compares them to an internal reference level produced via the on-chip bandgap reference circuit. When this level is exceeded, the gain of the front-end is reduced by controlling the feedback resistor Rf. A long time-constant integrator is used within the control loop of the AGC with a typical low frequency cut-off of 5 kHz.
Power Supply Rejection
An on-chip power supply rejection circuit is used to achieve both single-ended and differential rejection from the +5 V VCC rail. This stable DC reference minimizes the variation in the noise and bandwidth performance of the circuit due to power supply variation of +4.7 V to +5.3 V. The AC rejection ensures that performance is not degraded by noise on the power supply. The circuit achieves a power supply rejection on the outputs of 40 dB for both single-ended and differential operation, up to 100 kHz. The use of external decoupling will help to remove any unwanted signals at higher frequencies.
Output driver stage
The output driver acts as a buffer stage, capable of swinging up to 150 mVpk-pk into a 50 load (or 300 mVpk-pk differential into a 100 load). The small output swings allow ease of use with low voltage post amplifiers (e.g. 3.3 V parts). The output can be configured in a differential or single-ended mode. For differential operation, the pad ACGND is not wire bonded and the circuit provides a fully balanced 100 output, on the pins OUTP and OUTN. For single-ended operation, the ACGND pad is required to be wire bonded to an external capacitor
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Absolute Maximum Ratings
These are stress ratings only. Exposure to stresses beyond these maximum ratings may cause permanent damage to, or affect the reliability of the device. Avoid operating the device outside the recommended operating conditions defined below. Symbol VCC VIO IIO IIO VESD VESD Tstg Supply Voltage Voltage at any input or output Current sourced into any input or output except TZ_IN Current sourced into pin TZ_IN Electrostatic Discharge (100 pF, 1.5 k) except TZ_IN Electrostatic Discharge (100 pF, 1.5 k) pin TZ_IN Storage Temperature Parameter Min -0.7 -0.5 -20 -5 -2 -0.25 -65 Max 6.0 VCC+0.5 20 5 2 0.25 150 Unit V V mA mA kV kV C
Recommended Operating Conditions
Symbol VCC Tj Supply Voltage Operating Junction Temperature Parameter Min 4.7 -40 Typ 5.0 Max 5.3 95 Unit V C
DC Electrical Characteristics
Symbol ICC lagc Vin Vout Rout Supply Current AGC Threshold Input Bias Voltage Output Bias Voltage Output Resistance 4 VCC-3.2 2.9 35 50 VCC-3.0 VCC-2.7 3.5 65 Parameter Min Typ 39 Max 58 Unit mA A pk-pk V V
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AC Electrical Characteristics
Symbol BW (3dB) Tz Dri Voutmax Flf PSRR lOL Pol Nrms Parameter Small Signal Bandwidth at -3dB point Single-ended Transimpedance (50 on output, f = 50 MHz) Input Data Rate Maximum Differential Output Voltage Low Frequency Cut-off Power Supply Rejection Ratio (single-ended or differential) up to 100 kHz Input Current before overload (155 Mb/s NRZ data) Optical Overload Input Noise Current (in 100 MHz) 2600 +1.4 12 15 5 40 Min 150 11 10 15 20 155 300 Typ Max Unit MHz k Mb/s mV pk-pk kHz dB A pk-pk dBm nA rms
DC and AC electrical characteristics are specified under the following conditions : Supply Voltage (VCC).........................................4.7 V to 5.3 V Junction Temperature (Tj)..................................-40C to 95C Load Resistor (RL)...............................................50 AC coupled via 220 nF (single-ended) Photodetector Capacitance (Cd).......................0.5 pF Input bond wire inductance................................1 nH Photodetector responsivity.................................0.95 A/W Transimpedance (Tz) measured with 1 A mean photocurrent
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Bondpad Configuration
The bondpad center coordinates are referenced to the center of the lower left pad (pad 4). All dimensions are in microns (m). X Coordinate (m) -307.3 -307.3 -307.3 0 130.0 260.0 390.0 690.7 690.7 690.7 Y Coordinate (m) 679.0 549.0 315.0 0 0 0 0 155.0 285.0 679.0
Pad No. 1 2 3 4 5 6 7 8 9 10
Name VCC2 VCC1 TZ_IN VEE2 ACGND VEE1 VEE1 OUTN OUTP VCC1
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The diagram below shows the bondpad configuration of the SE1000W Transimpedance Amplifier. Note that the diagram is not to scale. All bondpads are 92 m x 92 m with a passivation opening of 82 m x 82 m. There are two VCC1 and two VEE1 pads for ease of wire bonding; these pad pairs are connected on-chip and only one pad of each type is required to be bonded out. Mechanical die visual inspection criteria per MIL-STD-883 Method 2010.10 Condition B Class Level B.
998.0 130.0
234.0
Top View
130.0 130.0 130.0 155.0 130.0 300.7 123.0 1250.0
925.0
126.0
307.3
315.0
394.0
Side View
All Dimensions in Microns (m)
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Applications Information
For optimum performance it is recommended that the device be used in differential mode with the circuit shown in the first diagram below. Note that the two VCC1 pads (2, 10) are connected on-chip, as are the VEE1 pads (6, 7), and only one pad of each type is required to be bonded out. However, in order to minimize inductance for optimum high speed performance, it is recommended that all power pads are wire bonded. The VEE2 and VCC2 pads are not connected on chip to VEE1 and VCC1 respectively, and must be bonded out separately. Connections for differential operation:
+5 V 1 VCC2 3 2 10 1 nF min
VCC1
TZ_IN
TZ Amplifier SE1000W
VEE1 6 7
9 OUTP OUTN ACGND 5 NC 8 To 50 O loads, AC coupled
PIN
VEE2 4
0 V or -ve bias
0V
Connections for single-ended operation:
+5 V 1 VCC2 3 2 10 1 nF min To 50 O load, AC coupled NC
VCC1
TZ_IN
TZ Amplifier SE1000W
VEE1 6 7
9 OUTP OUTN ACGND 5 1 nF 8
PIN
VEE2 4
0 V or -ve bias
0V
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Product Preview The datasheet contains information from the product concept specification. SiGe Semiconductor reserves the right to change information at any time without notification. Preliminary The datasheet contains information from the design target specification. SiGe Semiconductor reserves the right to change information at any time without notification. Final The datasheet contains information from the final product specification. SiGe Semiconductor reserves the right to change information at any time without notification. Production testing may not include testing of all parameters. Information furnished is believed to be accurate and reliable and is provided on an "as is" basis. SiGe Semiconductor Inc. assumes no responsibility or liability for the direct or indirect consequences of use of such information nor for any infringement of patents or other rights of third parties, which may result from its use. No license or indemnity is granted by implication or otherwise under any patent or other intellectual property rights of SiGe Semiconductor Inc. or third parties. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SiGe Semiconductor Inc. products are NOT authorized for use in implantation or life support applications or systems without express written approval from SiGe Semiconductor Inc. LightChargerTM is a trademark owned by SiGe Semiconductor. Copyright 2002 SiGe Semiconductor All Rights Reserved
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